The real constraint on edge AI isn't computing power,it's how fast data can move between the processor and memory. Flex Logix Technologies spent a decade solving this problem for programmable chips, then applied that same expertise to AI inference accelerators. The result is a fundamentally different approach to on-device AI that's now being integrated into Analog Devices' product portfolio following the company's acquisition in November 2024.

What's the Real Bottleneck in Edge AI Inference?

Most AI accelerators face a common problem: intermediate data generated during inference has to travel back and forth between the processor and external DRAM (dynamic random-access memory), the main memory system in most devices. This constant shuttling consumes far more power and time than the actual computation itself. It's like having a brilliant mathematician who has to walk to a distant library to retrieve each number before solving the next step.

Flex Logix's insight came from its existing business. The company had spent years building eFPGA (embedded field-programmable gate array) IP,essentially programmable logic blocks that customers could license and embed into their own chips. The key innovation was in the interconnect fabric, the wiring that connects different parts of the chip. Flex Logix had developed patented interconnect designs (ArrayLinx, RAMLinx, XFLX) that reduced routing complexity from 10 to 12 metal layers down to just 5 to 7, cutting the area and power needed for data movement.

When Cheng C. Wang, the company's SVP of Engineering, realized this same interconnect architecture could solve the DRAM bandwidth problem in AI inference, the nnMAX tile was born. Instead of sending intermediate data out to external memory, the architecture keeps it in on-chip SRAM (static random-access memory), which is much faster and more power-efficient.

How Does the nnMAX Architecture Actually Work?

Each nnMAX tile contains 1,024 multiply-accumulate units (MACs), the basic computational building blocks of neural networks, organized in clusters of 64. The weights,the learned parameters of the AI model,are stored locally in L0 SRAM right next to the computation. The ArrayLinx interconnect then performs a clever trick: it reconfigures thousands of wiring connections between layers in approximately one microsecond using partial reconfiguration, without requiring any changes to the underlying chip design. This means intermediate activations stay in SRAM rather than making expensive trips to external DRAM.

The InferX X1 chip, which shipped in 2021, arrays four nnMAX tiles in a 2x2 configuration plus an additional eFPGA block. Each tile delivers approximately 2.1 TOPS (tera-operations per second), giving the X1 8.4 TOPS total on TSMC's 16-nanometer process. Remarkably, the chip requires only a single DRAM connection, a direct consequence of keeping intermediate data in on-chip SRAM. The architecture scales to larger configurations without any changes to the underlying design, with implementations targeting over 100 TOPS for larger deployments.

The nnMAX Compiler ingests standard AI model formats like TensorFlow Lite or ONNX and maps them to the tile architecture, hiding the internal interconnect complexity from users entirely. Developers see a standard inference runtime, not the underlying reconfigurable wiring.

Why This Matters for the Broader Edge AI Industry

Flex Logix's approach represents a significant shift in how the industry thinks about AI accelerator design. For years, systolic arrays (a specific type of regular, grid-like processor architecture) dominated AI chip design because they seemed efficient. But Flex Logix demonstrated that FPGA-style programmable interconnect, historically dismissed as too expensive in area and power, could actually be the mechanism that eliminates the DRAM bandwidth problem entirely.

The company's $82 million in funding and eventual acquisition by Analog Devices signals that major semiconductor companies now see embedded inference IP as a core capability for their SoCs (system-on-chip designs), not an optional add-on. ADI's strategic rationale is clear: the nnMAX IP core provides a scalable inference accelerator block that ADI can embed in its own signal processing SoCs, while the eFPGA IP adds reconfigurability to ADI's industrial and communications portfolio.

Steps for Evaluating On-Device Inference Architectures

• Assess DRAM Bandwidth Constraints: Evaluate whether your edge AI application is bottlenecked by memory bandwidth rather than raw compute throughput. If intermediate data movement is consuming most of the power and latency, an architecture designed to minimize DRAM traffic becomes critical.
• Consider Scalability Without Redesign: Look for inference IP that can scale from smaller configurations to larger ones without requiring full chip redesigns. Flex Logix's NxN tile scalability without GDS (design file) changes is a significant advantage for companies planning multiple product generations.
• Evaluate Multi-Foundry Portability: For defense, aerospace, and other regulated industries, the ability to manufacture the same design across multiple foundries (TSMC, GlobalFoundries, etc.) reduces supply chain risk and provides flexibility in procurement.

Flex Logix demonstrated the InferX X1 on both TSMC 16-nanometer and GlobalFoundries 12LP processes under a US government agreement, giving the IP multi-foundry portability that matters for critical applications.

What Happened to Flex Logix After the Acquisition?

Analog Devices acquired Flex Logix on November 11, 2024, with financial terms undisclosed. While the company had generated approximately $4.5 million in annual revenue at the time of acquisition, that figure was modest relative to the $82 million raised across four funding rounds. However, revenue-per-employee metrics were typical for early-stage chip companies still in initial deployment cycles.

The acquisition removes the stand-alone company risk and provides the nnMAX IP with a distribution channel through ADI's extensive SoC and module portfolio. For ISVs (independent software vendors) and silicon teams evaluating inference IP, nnMAX under ADI is worth tracking because the architecture survived acquisition, which is the critical filter for long-term viability.

"CPUs are becoming increasingly important as AI systems evolve into heterogeneous computing environments, where execution depends not only on NPU performance, but on the seamless coordination between CPUs and NPUs," said Dr. Ken Phua, CEO of Acrab.

Dr. Ken Phua, CEO of Acrab

This observation from a competing edge AI company underscores a broader industry shift: as inference moves on-device, the bottleneck is increasingly about how different processor types coordinate, not just raw neural processing unit (NPU) throughput. Flex Logix's interconnect-centric approach directly addresses this coordination challenge.

The inflection point Flex Logix represents is now visible across the industry. Architects are revisiting routing topology specifically for AI dataflows rather than defaulting to traditional systolic array designs. ADI's acquisition confirms that major analog IC companies see embedded inference IP as a core SoC capability, not an optional block. For the edge AI industry, that's a significant signal about where the next generation of on-device intelligence will be built.