IBM has developed a sub-nanometer chip technology that could fundamentally change how densely transistors fit onto silicon, potentially delivering 50 percent higher performance or 70 percent greater energy efficiency than current cutting-edge designs. The company announced its new 0.7-nanometer (7 Angstrom) process node, which can pack nearly 100 billion transistors onto a silicon die the size of a fingernail, almost double the density of the 2-nanometer technology IBM unveiled back in 2021.

What Makes IBM's Nanostack Architecture Different?

IBM's breakthrough centers on a three-dimensional nanostack design that stacks transistors vertically in a novel way. Unlike traditional approaches, the transistors in the upper layer are staggered or offset from those below, allowing the front and back sides of each transistor to be contacted independently for signal and power delivery. This architecture represents a meaningful leap forward in how the semiconductor industry can continue shrinking chips beyond the limits of conventional two-dimensional designs.

The innovation relies on single dielectric bonding, a key technique IBM developed that allows the channel materials in the top and bottom transistor layers to be optimized independently. This flexibility opens doors for multiple applications across different chip types and use cases.

"Nanostack is not one innovation. It is actually a device platform that can enable the future of scaling for another decade beyond nanosheet, as you can see from our technology roadmap all the way to 1 Angstrom," stated Jay Gambetta, director of IBM Research and IBM Fellow.

Jay Gambetta, Director of IBM Research and IBM Fellow at IBM

How Could This Technology Be Used in Real-World Applications?

• AI Accelerators: IBM hints that nanostack could power future artificial intelligence chips, particularly those requiring larger on-chip memory to improve performance and efficiency.
• CPUs and GPUs: The architecture supports central processing units and graphics processing units, the workhorses of modern computing.
• Mobile Chips: Smartphone and tablet processors could benefit from the higher transistor density and improved power efficiency.
• Memory Systems: Static random-access memory (SRAM), a critical component in AI chips, showed a 40 percent scaling improvement in initial experiments, addressing a bottleneck in AI chip design.

Gambetta highlighted the significance for AI applications, noting that many AI chips rely on larger SRAM to scale effectively. The ability to make transistors more efficient, consume less power, and fit more of them onto a single die directly addresses this challenge.

When Will This Technology Reach Production?

IBM claims its new process node could be used to produce commercial chips within five years, positioning it ahead of competitors like Intel and TSMC, which are preparing 1.4-nanometer nodes for production in 2028. However, IBM itself no longer manufactures chips. Instead, the company licenses its technology to foundries, the specialized manufacturers that produce chips for other companies.

When asked which foundry might adopt the sub-nanometer process, Huiming Bu, vice president of Silicon Technology Research and Development at IBM, explained that the nanosheet architecture IBM invented is already being used by all leading foundries. Currently, IBM is focusing on helping Rapidus, a government-backed Japanese semiconductor foundry, achieve success in bringing 2-nanometer manufacturing capability to Japan.

"I'm not going to talk about a business model, but it's being adopted by all leading foundries. But today, we are focusing on helping Rapidus to be successful in bringing up 2 nanometer manufacturing capability in Japan," explained Huiming Bu.

Huiming Bu, Vice President of Silicon Technology Research and Development at IBM

What Does This Mean for the Semiconductor Industry?

IBM's nanostack represents a significant shift in how the industry approaches the physical limits of chip miniaturization. For years, semiconductor companies have relied on making transistors smaller and smaller, a process governed by Moore's Law, which predicts that the number of transistors on a chip doubles roughly every two years. However, as transistors approach atomic scales, traditional scaling becomes increasingly difficult and expensive.

By stacking transistors vertically and optimizing each layer independently, IBM has found a way to continue improving chip performance without simply shrinking everything proportionally. This approach could extend the industry's ability to improve chips for another decade, buying time for researchers to develop entirely new computing paradigms beyond traditional silicon transistors.

The nanostack design also addresses a critical concern in modern chip design: power consumption. As AI workloads become more demanding, the ability to deliver 70 percent greater energy efficiency than current 2-nanometer designs could significantly reduce the electricity costs of running large data centers and AI systems. This efficiency gain matters not just for performance, but for the environmental and economic sustainability of computing infrastructure.

IBM's detailed roadmap, which extends all the way to 0.1-nanometer technology over the next decade, signals that the company believes this vertical stacking approach can continue delivering improvements long after conventional horizontal scaling reaches its limits. The company has published its findings in a peer-reviewed paper available through the IEEE, allowing the broader research community to build on this work.