A consortium of researchers has achieved a major milestone in shrinking transistors to atomic scales, demonstrating complementary 2D-material transistors at a 50-nanometer pitch on full-size 300-millimeter wafers. The breakthrough, presented this week at the IEEE/JSAP Symposium on VLSI Technology and Circuits, shows that exotic materials like molybdenum disulfide and tungsten diselenide can work together in practical manufacturing processes, not just in laboratory prototypes.

The collaboration between imec, ASML, and TSMC represents a critical step toward the next generation of chip manufacturing. For more than a decade, researchers have studied 2D transition metal dichalcogenides as potential replacements for silicon when transistors reach their physical limits. What makes this result different is that both n-type and p-type transistors were integrated together on a single wafer using standard manufacturing equipment, rather than as isolated experimental devices.

What Makes This Transistor Breakthrough Different?

The key innovation lies in how the researchers solved a fundamental problem that has blocked 2D transistor scaling for years: contact resistance. When you shrink a transistor to atomic thickness, the electrical connection between the metal contacts and the ultra-thin channel becomes a bottleneck. The metal tends to pin the semiconductor's Fermi level, creating a barrier that blocks current flow. Previous attempts compensated by using large contact areas, but that defeats the purpose of scaling down.

The imec-ASML-TSMC team inverted the traditional manufacturing order. Instead of depositing metal onto the fragile 2D film after the channel is in place, they patterned tungsten-filled contact trenches first, then transferred the 2D channel material on top. This "reverse" thin-film-transistor flow created a bottom-contact geometry that dramatically improved performance.

"For the first time, we achieved 50nm CPP, a metric determined by both the gate length and source/drain contact length, without affecting the performance of the 2D n and pFETs," said Gouri Sankar Kar, vice president of R&D for compute and memory device technologies at imec.

Gouri Sankar Kar, Vice President of R&D for Compute and Memory Device Technologies at imec

The transistors demonstrated impressive performance metrics. The researchers achieved channel lengths as short as 28 nanometers using a single extreme ultraviolet (EUV) exposure, with 94% of the integrated transistors switching correctly and an on/off current ratio exceeding 100,000. For context, a 50-nanometer pitch is tighter than Intel's 10-nanometer-class node, which used a 54-nanometer contacted gate pitch.

How Does This Fit Into the Semiconductor Roadmap?

The semiconductor industry has a clear timeline for when 2D materials become relevant to production chips. According to imec's long-range roadmap, 2D atomic channels are not expected until after 2030, with complementary field-effect transistors (CFETs) anticipated around 2033 and a full transition to 2D-semiconductor channels closer to 2041. The broader industry roadmap, tracked by the International Roadmap for Devices and Systems (IRDS), pencils in 2D channels as early as 2034 at the 0.7-nanometer node.

This timeline matters because TSMC only began volume production of its first gate-all-around node, N2, late last year. The CFET, which stacks n-type transistors over p-type transistors, is the next step before 2D channels become relevant to logic chips. The engineering demonstrated this week narrows the work to manufacturing problems rather than fundamental questions about whether the devices can be built at scale.

Steps to Understanding 2D Transistor Development

• Material Selection: The n-channel devices use molybdenum disulfide (MoS2), while p-channel devices use tungsten diselenide (WSe2) or tungsten disulfide (WS2), each chosen for specific electrical properties in complementary circuits.
• Manufacturing Integration: Both transistor types were built together on a standard 300-millimeter process flow using single-patterning EUV lithography, demonstrating compatibility with existing fab infrastructure.
• Performance Validation: The devices reached active widths down to 75 nanometers with equivalent oxide thickness near 2 nanometers, and both polarities turned fully off at zero gate voltage, confirming proper switching behavior.
• Contact Engineering: The reverse thin-film-transistor flow places metal contacts beneath the 2D channel, solving the contact resistance problem that previously blocked pitch scaling.

While the demonstration is impressive, several challenges still separate it from a production process. The integration is quasi-CMOS, meaning the n- and p-type materials are placed side by side by transferring films onto the wafer, not grown together in a single monolithic flow. Wafer-scale, residue-free transfer at production throughput remains unsolved. Beyond that, fab-compatible low-resistance contacts, controllable doping, and long-term reliability data all need to be addressed.

"The collaboration's aim is de-risking the lab-to-fab transition for novel channel materials," explained Dr. Min Cao, vice president and chief technology officer at TSMC.

Dr. Min Cao, Vice President and Chief Technology Officer at TSMC

Samsung has already demonstrated wafer-scale growth of single-crystal molybdenum disulfide, and Intel has run its own 300-millimeter 2D-material program with imec, showing that major chipmakers are investing in this technology path. However, the first production role for 2D channels is likely to be modest back-end or wafer-backside devices, not high-performance logic.

The significance of this work extends beyond the immediate technical achievement. It shows that the semiconductor industry can move beyond silicon's physical limits by combining novel materials with advanced manufacturing techniques. The collaboration between equipment maker ASML, research institute imec, and foundry TSMC demonstrates how the ecosystem is preparing for the post-silicon era, even though volume production remains years away. For companies like Samsung and Intel watching from the sidelines, the message is clear: the race to master 2D materials is already underway.