Nvidia CEO Jensen Huang acknowledged Huawei's new chip design approach as a legitimate breakthrough, but argued it relies on techniques that leading chipmakers like TSMC have already mastered. The comment came as Huawei unveiled its "Tau Scaling Law," a strategy to boost chip performance by improving data transmission speed rather than continuing to shrink transistors, a shift driven partly by U.S. export restrictions on advanced manufacturing equipment.

What Is Huawei's New Chip Strategy?

Huawei this week introduced LogicFolding, a technique that arranges logic, analog, and memory circuits in stacked, tightly connected structures to improve efficiency and speed. The approach represents a departure from the semiconductor industry's decades-long reliance on Moore's Law, which holds that the number of transistors on a microchip doubles roughly every two years.

The Chinese company faces a real constraint: since 2019, it has been barred from importing ASML's most advanced extreme ultraviolet (EUV) lithography machines, which are essential for manufacturing cutting-edge chips with smaller transistors. Huawei's new strategy sidesteps this limitation by focusing on speed and efficiency rather than miniaturization.

"This is a breakthrough for Huawei, but it's not a threat for TSMC. TSMC has been using die stacking and 3D packaging for how long now? Almost 10 years. And so TSMC's technology is very advanced," said Jensen Huang, Nvidia CEO.

Jensen Huang, CEO at Nvidia

Huang's assessment reflects the reality that advanced packaging and 3D stacking are not new concepts in the chip industry. Memory chip makers like SK Hynix and Samsung Electronics already use advanced 3D stacking to produce multi-layer memory chips, a critical component of artificial intelligence chipsets.

What Are the Real Challenges for Huawei's Approach?

While Huawei claims its new Kirin smartphone chip will achieve a 41% improvement in power efficiency and a nearly 13% increase in peak operating speed compared to its single-layer design, independent verification remains elusive. Analysts and industry experts have raised several concerns about scaling the technology:

• Manufacturing Complexity: Stacking multiple chip layers increases power density and risks overheating chips, requiring new cooling solutions for everything from smartphones to large artificial intelligence data centers.
• Design Tool Requirements: The approach demands entirely new electronic design automation (EDA) software tools suited to folded chip architectures, a significant barrier since mainstream EDA vendors like Cadence Design Systems and Synopsys would need to rebuild their software.
• Production Yields and Costs: Bernstein analysts cautioned that production yields and manufacturing costs represent major adoption barriers, and Huawei has not yet disclosed yield rates or cost comparisons with rival chips made using more advanced process nodes.

Lian Jye Su, chief analyst at tech research firm Omdia, emphasized the lack of concrete evidence: "There's nothing concrete that can be independently verified or benchmarked against other players at the moment".

How Does This Fit Into the Broader AI Chip Race?

Huawei's pivot comes as the global semiconductor industry grapples with multiple bottlenecks in artificial intelligence infrastructure. While Huawei focuses on speed through stacking, other companies are pursuing different solutions. Nvidia, for instance, is investing billions of dollars into photonics technology, which uses light instead of electricity to transfer data between chips and systems, potentially solving data transfer inefficiencies.

Since March, Nvidia has announced major investments in photonics companies, including $2 billion each into Lumentum, Coherent, and Marvell, plus $500 million into Corning and participation in optics startup Ayar Labs' $500 million funding round. These investments reflect the industry's recognition that data communication between chips is becoming a critical constraint on artificial intelligence performance.

"One of the main bottlenecks for the performance of AI models is the speed of communication between chips and between chip servers," explained Gil Luria, head of technology research at D.A. Davidson.

Gil Luria, Head of Technology Research at D.A. Davidson

The competition between different technological approaches, whether Huawei's speed-focused architecture, TSMC's advanced packaging, or Nvidia's photonics investments, underscores how the artificial intelligence boom is driving innovation across multiple fronts. However, Huang's comments suggest that established players with years of experience in advanced packaging maintain a significant technological advantage, even as newer competitors attempt to leapfrog traditional manufacturing constraints.