Meta has unveiled a major leap in custom AI silicon with its MTIA 400 accelerator, achieving 46 times greater memory bandwidth than its previous generation while introducing support for lower-precision computing that dramatically boosts performance. The company presented the chip at Hot Chips 2026, showcasing how building specialized hardware for specific AI workloads can outperform general-purpose graphics processors (GPUs) and reduce operational costs.

Why Is Meta Building Its Own AI Chips?

Meta faces a unique challenge: the company needs to generate millions of personalized recommendations every day across its platforms. This type of work, known as Deep Learning Recommendation Model (DLRM) training, is extremely memory-intensive and doesn't play well with traditional GPUs. Rather than continuing to buy expensive commodity hardware from major vendors and paying steep margins, Meta decided to design chips specifically optimized for its workloads.

The company's first custom chip, the MTIA 300, proved the concept worked. It matched GPU performance at a competitive total cost of ownership while achieving over 1.8 times speedup in both forward and backward model propagation. Building on that success, Meta developed the MTIA 400 as a broader inference accelerator capable of handling generative AI workloads beyond just recommendations.

What Makes the MTIA 400 a Major Upgrade?

The MTIA 400 represents a significant architectural redesign. The chip uses multiple types of chiplets, including compute, system-on-chip (SoC), and input/output (I/O) chiplets, all working together to handle massive AI inference tasks. The most striking performance gains come from three key improvements:

• Memory Bandwidth: The chip delivers 9.4 terabytes per second of memory bandwidth through eight stacks of HBM3e memory, providing 46 times more bandwidth than the MTIA 200 inference accelerator it replaces.
• Compute Precision Support: The MTIA 400 introduces hardware support for MXFP4, a lower-precision format that allows the chip to perform 12 petaFLOPS of FP4 compute, enabling faster processing of large language models without sacrificing accuracy.
• Scaling Capability: Up to 72 individual MTIA 400 accelerators can be connected in a single domain, allowing Meta to scale inference workloads across massive clusters while maintaining efficient communication.

The chip also includes 15 times more FP16 compute performance compared to the MTIA 200, alongside five times more static random-access memory (SRAM) bandwidth. These improvements directly address the bottlenecks that make generative AI inference so resource-intensive.

How Does Meta's Custom Silicon Compare to GPUs?

Meta's engineering team identified specific weaknesses in using GPUs for their workloads. Memory utilization and floating-point operations per second (FLOPS) utilization both present bottlenecks when training recommendation models at scale. The MTIA 300 solved this by pairing 72 processing elements with 216 gigabytes of HBM3e memory, creating a chip purpose-built for the job.

The MTIA 400 takes this further by introducing specialized hardware units designed for specific operations. Each processing element contains dedicated fixed-function blocks, including a special function unit that handles non-linear operations and data type conversions. The chip can also perform a gather operation, pulling 64 elements from memory in a single clock cycle, which is critical for recommendation systems that need to fetch embeddings quickly.

What's Next for Meta's AI Chip Roadmap?

Meta has already mapped out the future of its custom silicon. The company plans to release four generations of accelerators: the MTIA 300, 400, 450, and 500. The MTIA 450 will focus on enhanced generative AI inference performance, while the MTIA 500 will push even further on scaling, supporting larger scale-up domains beyond the current 72-accelerator limit.

This roadmap reflects a broader industry trend where major AI companies are moving away from relying solely on Nvidia's GPUs and building specialized hardware tailored to their specific needs. For Meta, the investment in custom silicon directly supports its massive infrastructure spending on AI inference, which will power recommendation systems, content moderation, and generative AI features across its platforms.

How to Understand Meta's AI Chip Architecture

• Chiplet Design: The MTIA 400 uses multiple specialized chiplets rather than a monolithic design, allowing Meta to optimize each component for its specific function while improving manufacturing yield and flexibility.
• Network-on-Chip Fabric: A two-dimensional mesh network connects all processing elements and messaging elements, implementing congestion control mechanisms to prevent data bottlenecks when moving information between compute units.
• Embedded CPU Cores: Each processing element contains two RISC-V CPU cores for general-purpose vector operations, while messaging elements have their own RISC-V cores to orchestrate data movement and collective operations across the chip.
• Multi-Level Memory Hierarchy: The chip combines high-bandwidth HBM3e stacks for main memory, embedded SRAM for fast access, and specialized embedding caches that keep frequently accessed data close to compute units.

The MTIA 400's architecture reflects Meta's deep understanding of its own workloads. By building silicon specifically designed for recommendation systems and generative AI inference, the company can achieve performance and efficiency levels that general-purpose accelerators cannot match. As AI infrastructure costs continue to climb, this strategy of vertical integration into chip design is likely to become increasingly common among large technology companies managing massive data centers.