The semiconductor industry is abandoning the strategy that powered computing for six decades. On May 25, 2026, Huawei announced a fundamental shift away from Moore's Law, the principle that transistor counts double roughly every two years. Instead of making transistors smaller, the industry is now focusing on making signals travel faster through chips. This pivot reflects a hard physical reality: transistors are approaching the size of individual silicon atoms, and shrinking them further would cause electrons to escape through quantum tunneling.

Why Is Moore's Law Finally Hitting Its Limit?

For 60 years, the entire semiconductor supply chain, from chip designers to equipment makers like ASML, has operated under Moore's Law as an unspoken covenant. The law promised that each generation of chips would pack more transistors into the same space at lower cost. But the physics no longer cooperates. Today's most advanced chips have gate widths measured in just a dozen silicon atoms. Push smaller, and the quantum world takes over.

The collapse actually began around 2005, when Dennard Scaling, a companion principle that promised heat generation would stay manageable as chips shrank, broke down. Engineers discovered that tiny transistors generate disproportionate heat, forcing Intel and others to abandon the race for higher clock speeds and pivot to multi-core designs instead. The smartphone era temporarily extended Moore's Law's relevance, but entering the single-digit nanometer range has made each step forward exponentially more expensive and difficult. A single 3-nanometer wafer factory now costs tens of billions of dollars, and only a handful of companies worldwide can afford one.

What Is Tao Law, and How Does It Work?

He Tingbo, president of Huawei's Semiconductor Business Unit, introduced a new framework called Tao Law, named after the Greek letter tau, which represents the "time constant" in circuit theory. The core idea is elegantly simple: instead of shrinking transistors, reduce the time it takes for electrical signals to travel through the chip. In circuit design, signals move along metal wires that have resistance. Longer wires mean greater resistance and slower signals. By compressing the time constant, chips become faster and more efficient without requiring a smaller manufacturing process.

He Tingbo decomposed tau into four layers where compression can occur. Each layer offers different optimization opportunities:

• Transistor Layer: Improvements at the individual transistor level, though this is where traditional process shrinking happens.
• Circuit Layer: Optimizing how transistors connect and signal pathways within circuits to reduce propagation delay.
• Chip Layer: Redesigning the overall chip architecture to minimize signal travel distances and latency.
• System Layer: Improving how multiple chips communicate and coordinate at the system level.

Huawei has already begun implementing this approach. The company has mass-produced 381 chips over the past six years using this methodology. The new-generation Kirin chips launching this autumn will achieve more than a 50% jump in transistor density without changing the manufacturing process. By 2031, Huawei plans to reach transistor density equivalent to a 1.4-nanometer process using Tao Law principles alone.

How Are Other Chip Giants Pursuing This Strategy?

Huawei's announcement formalizes a direction the entire industry has been quietly exploring for nearly a decade. NVIDIA, AMD, and TSMC have all launched breakthrough initiatives that align with Tao Law's core principle: optimize what you can't shrink anymore.

NVIDIA's approach centers on interconnection bandwidth. In 2016, the company introduced NVLink, a high-speed inter-GPU communication bus designed to solve the bottleneck of data transmission between graphics processors. Jensen Huang, NVIDIA's founder and CEO, recognized that as individual GPU performance plateaued, the ability to link multiple GPUs together would become the real competitive advantage. This bet proved prescient. From the first-generation NVLink to the fifth-generation Blackwell architecture released in 2024, inter-GPU interconnect bandwidth has increased by dozens of times. The GB200 NVL72 configuration connects 72 GPUs using fifth-generation NVLink, achieving two-way interconnect bandwidth of 1.8 terabytes per second per GPU, with total NVLink domain bandwidth exceeding 130 terabytes per second. NVIDIA even uses NVLink-C2C to directly solder GPUs and CPUs together, allowing them to share unified memory.

"At the first press conference, Jensen Huang was also more willing to spend time talking about 'interconnection' rather than just 'computing power'," noted He Tingbo in his analysis of industry trends.

He Tingbo, President of Semiconductor Business Unit, Huawei

AMD took a different path with chiplets. Starting with the Zen 2 architecture in 2019, AMD split processors into multiple smaller chips manufactured separately and then packaged together. This approach bypassed the photomask size limit and improved manufacturing yield. AMD extended this concept further in AI chips. The MI300X, released in late 2023, uses TSMC's 3D packaging technology to vertically stack multiple computing and input/output dies. A single package integrates 153 billion transistors and 192 gigabytes of HBM3 memory, achieving integration levels that a single monolithic chip could not.

TSMC, the world's leading chip manufacturer, has shifted its strategic narrative away from pure process shrinkage. While the company still pursues advanced nodes, the proportion of advanced packaging in its capital expenditure and strategic focus has increased rapidly since 2023. CoWoS packaging technology, which tightly couples GPU chips with HBM memory to maximize bandwidth density, has become a production bottleneck and a critical component of AI chip shipments. At the 2026 technology forum, TSMC announced a three-layer AI platform architecture: computing at the bottom, packaging integration in the middle, and photonic interconnection at the top. The COUPE technology uses optical signals to replace traditional electrical interconnects, further reducing signal propagation delays.

What Does This Mean for the Future of Computing?

The shift from Moore's Law to Tao Law represents a fundamental reorientation of the semiconductor industry. For half a century, the industry's power structure was determined by who could produce chips with the most advanced process nodes. That hierarchy is dissolving. Companies that excel at system-level optimization, interconnection design, and packaging innovation will compete on equal footing with those pushing process boundaries.

This transition also changes the economics of chip development. Building a 3-nanometer fab requires tens of billions of dollars and years of construction. Optimizing interconnection, chiplet design, and packaging requires different expertise but lower capital barriers. Smaller companies and regional manufacturers may find new opportunities in this landscape. The industry's underlying belief system, which has guided investment and strategy for 50 years, is being rewritten in real time.